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Job Description:

The System Engineering group is responsible for ensuring that the end products operate fully in their intended applications. This involves the planning, design, integration, test and documentation of a complete system level platform used to test the prototype System-on-Chip (Soc) along with associated Firmware (FW) & Software (SW). The Validation Engineer works in parallel with IC and FW engineers to design an appropriate test system. This can involve test FW development, FPGA VHDL/Verilog coding, digital/analog board designs and test script coding.

Using these systems, together with the latest communication analyzers and test equipment, the Validation Engineer will execute a Feature Test Plan that fully validates all features of the prototype SoC and associated FW. The Validation Engineer will be involved with existing and newly drafted standards used in Cloud Storage, Data Center, and other high performance computing applications such as including PCIe, NVMe and others.

Responsibilities could include but are not limited to the following:

As a Validation Engineer Intern, you would be assigned one or more of these activities:

You will work as part of a team to develop, execute and document a series of Feature Tests that will fully validate the operation of the prototype SoC and Firmware as part of the overall system. These feature tests will exercise the various functional blocks of a prototype IC & associated FW/SW to ensure the system meets designed criteria and industry standards.

Requirements/Qualifications:

Qualifications:

Desirable:

Travel Time: